Method of generating initializing signal in semiconductor memory device

ABSTRACT

A method for generating an initializing signal capable of preventing inner circuits installed in a semiconductor memory device from being initially unstably operated due to the application of external electric power. The method includes the steps of: (a) receiving a precharge command for precharging the semiconductor memory device; (b) activating the initializing signal to a first level in response to the received precharge command; (c) receiving a refresh command for refreshing the semiconductor memory device after receipt of the precharge command; (d) receiving a mode set command for setting an operational mode of the semiconductor memory device after receipt of the refresh command; and (e) deactivating the initializing signal to a second level in response to the received mode set command. An alternative method includes the step of (a) receiving a mode set command foe initializing an inner circuit in a semiconductor memory device and (b) generating a control signal in response to the received mode set command and using the control signal as the initializing signal.

This application is a continuation in part of U.S. patent applicationSer. No. 10/187,718 filed on Jul. 1, 2002, now pending, which claimspriority from Korean application No. 2001-43111 filed Jul. 18, 2001 andKorean priority No. 2002-38893 filed Jul. 5, 2002 is herein incorporatedby reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, and moreparticularly, to a method of generating an initializing signal capableof preventing unstable operations of inner circuits when a semiconductormemory device is powered on.

2. Description of the Related Art

Power-up is to apply external electric power to a semiconductor memorydevice for operating the same. A semiconductor memory device includes aninitializing circuit in order to prevent inner circuits from beingunstably operated during power-up. Here, the unstable operations of theinner circuits mean that whether data in a circuit is logic ‘high’ orlogic ‘low’ is difficult to be determined in a power-up operationsection because external electric power is not completely stabilized.The unstable operations of the inner circuits can be prevented bylatching the inner circuits through an initializing signal that istemporarily logic ‘high’ but drops to logic ‘low’ during the power-up.

FIG. 1 is a view of an initializing circuit 100 capable of preventingunstable operations of inner circuits of a semiconductor memory deviceupon power-up. Referring to FIG. 1, the initializing circuit 100includes a PMOS transistor MP1, a capacitor CAP, a resistor R1 andinverters I11 through I13. In the operation of the initializing circuit100, an initializing signal VCCHB output from the initializing circuit100 becomes larger due to an increase in a voltage level when externalelectric power EVC from an outer source is applied to the initializingcircuit 100 and the voltage level of the external electric power EVC israised. If the voltage level of the external electric power EVC is abovea predetermined level, the voltage of the initializing circuit 100 isadjusted so that a first node N11 becomes a logic ‘high’ level. Once thefirst node N11 is recognized as logic ‘high’, the initializing signalVCCHB is generated to be logic ‘low’ by the inverters I11 through I13.Here, the initializing pulse signal VCCHB is used for preventingunstable operation of the inner circuits of a semiconductor memorydevice during power-up operation.

FIG. 2 shows an example of a method of initializing the inner circuitsof a semiconductor memory device using an initializing signal. In theoperation of the circuit shown in FIG. 2, an input signal IN is inactiveduring power-up, and therefore a first node N21 is in an unstable state.At this time, when a logic ‘high’ initializing signal VCCHB is input, aPMOS transistor MP2 is turned on by an inverter I21 and the first nodeN21 is latched to the logic ‘high’ level and stabilized. As a result,variations in an output signal OUT can be prevented. When theinitializing signal VCCHB is transited to the logic ‘low’ level, thePMOS transistor MP2 is turned off and the first node N21 remains latchedto the logic ‘high’ level. As described above, the initializing signalVCCHB sets each of the nodes of the inner circuit of a semiconductormemory device to a predetermined logic level upon power-up.

However, the initializing circuit 100 has problems in that it has alarge layout area and consumes power while the semiconductor memorydevice operates, even after the initializing signal VCCHB is generated.Further, the current trend is to reduce the voltage of the externalelectric power EVC (to conserve power and increase speed), thuslessening a voltage level of the initializing signal VCCHB. This causesthe initializing signal VCCHB to fail to fulfill the function ofpreventing unstable operation of the inner circuits.

In contrast, a method of generating an initializing signal according tothe present invention can reduce the layout area and power consumptionof an initializing circuit during power-up.

SUMMARY OF THE INVENTION

To solve the above problems, it is an objective of the present inventionto provide a method of generating an initializing signal capable ofreducing the layout area and power consumption of an initializingcircuit during power-up.

Accordingly, to achieve one aspect of the above objective, there isprovided a method of generating an initializing signal, the methodincluding the steps of: (a) receiving a precharge command forprecharging the semiconductor memory device; (b) activating theinitializing signal to a first level in response to the receivedprecharge command; (c) receiving a refresh command for refreshing thesemiconductor memory device after receipt of the precharge command; (d)receiving a mode set command for setting an operational mode of thesemiconductor memory device after receipt of the refresh command; and(e) deactivating the initializing signal to a second level in responseto the received mode set command.

To achieve another aspect of the above objective, there is provided amethod for generating an initializing signal including the steps of: (a)receiving a precharge command for precharging the semiconductor memorydevice; and (b) generating an automatic pulse as an initializing signalin response to the received precharge command.

To achieve still another aspect of the above objective, there isprovided a method for generating an initializing signal including thesteps of: (a) receiving a mode set command for setting an operationalmode of the semiconductor memory device; and (b) generating an automaticpulse as an initializing signal in response to the received mode setcommand.

To achieve still another aspect of the above objective, there isprovided a method for generating an initializing signal capable ofpreventing initial unstable operations of inner circuits installed in asemiconductor memory device which includes an initializing circuit forpreventing the inner circuits from being initially unstably operated dueto the application of external electric power. The method includes thesteps of: (a) the initializing circuit generating a pre-initializingsignal in response to the external electric power; (b) receiving a modeset command for setting an operational mode of the semiconductor memorydevice; and (c) generating an automatic pulse in response to thepre-initializing signal and the received mode set command. The methodmay further include step (d) of turning off the initializing circuit inresponse to the generated initializing signal.

To achieve still another aspect of the above objective, there isprovided a method of turning off an initializing circuit for generatingan initializing signal capable for preventing inner circuits installedin a semiconductor memory device from being initially unstably operateddue to application of external electric power, according to a fifthembodiment of the present invention. The method includes the steps of:(a) the initializing circuit generating an initializing signal inresponse to the external electric power; (b) receiving a prechargecommand or precharging the semiconductor memory device; and (c) turningoff the initializing circuit in response to the precharge command.

To achieve still another aspect of the above objective, there isprovided a method of turning off an initializing circuit for generatingan initializing signal capable of preventing inner circuits installed ina semiconductor memory device from being initially unstably operated dueto application of external electric power. The method includes the stepsof: (a) the initializing circuit generating an initializing signal inresponse to the outer source of electric power; (b) receiving a mode setcommand for setting an operational mode of the semiconductor memorydevice; and (c) turning off the initializing circuit in response to themode set command.

To achieve still another aspect of the above objective, there isprovided a method of generating an initializing signal for initializingthe inner circuits in a semiconductor memory device, the methodincluding the steps of: (a) receiving a mode set command forinitializing the inner circuits; and (b) generating a control signal inresponse to the received mode set command and using the control signalas the initializing signal.

The mode set command is a signal applied to the semiconductor memorydevice via an external pin. Also, the mode set command is a moderegister set (MRS) command in a synchronous dynamic random access memory(DRAM), and a Write Column address strobe (CAS) Before Row addressstrobe (RAS) (WCBR) in an asynchronous dynamic random access memory(DRAM).

To achieve still another aspect of the above objective, there isprovided a method of generating an initializing signal for initializingthe inner circuits in a semiconductor memory device, the methodincluding the steps of: (a) receiving a precharge command forprecharging the semiconductor memory device; (b) receiving a mode setcommand for initializing the inner circuit after receipt of theprecharge command; and (c) generating a control signal in response tothe received mode set command, and using the control signal as theinitializing signal. The mode set command is a signal applied to thesemiconductor memory device via an external pin. Also, the mode setcommand is a mode register set (MRS) command in a synchronous dynamicrandom access memory (DRAM), and a Write Column address strobe (CAS)Before Row address strobe (RAS) (WCBR) in an asynchronous dynamic randomaccess memory (DRAM).

BRIEF DESCRIPTION OF THE DRAWINGS

The above objective and advantages of the present invention will becomemore apparent by describing in detail preferred embodiments thereof withreference to the attached drawings in which:

FIG. 1 is a circuit diagram of an initializing circuit capable ofpreventing unstable operations of inner circuits during power-up;

FIG. 2 is a circuit diagram of an initializing circuit that utilizes aninitializing signal;

FIG. 3 is a flowchart illustrating a method of generating aninitializing signal according to a first embodiment of the presentinvention;

FIG. 4 is a flowchart illustrating a method of generating aninitializing signal according to a second embodiment of the presentinvention;

FIG. 5 is a flowchart illustrating a method of generating aninitializing signal according to a third embodiment of the presentinvention;

FIG. 6 is a flowchart illustrating a method of generating aninitializing signal according to a fourth embodiment of the presentinvention;

FIG. 7 is a flowchart illustrating a method of turning off aninitializing circuit according to a fifth embodiment of the presentinvention;

FIG. 8 is a flowchart illustrating a method of turning off aninitializing circuit according to a sixth embodiment of the presentinvention;

FIG. 9 is a flowchart illustrating a method of generating aninitializing signal according to a seventh embodiment of the presentinvention;

FIG. 10 is a flowchart illustrating a method of generating aninitializing signal according to an eighth embodiment of the presentinvention;

FIG. 11 is a block diagram for explaining the method illustrated in FIG.9; and

FIG. 12 is a waveform diagram of the initializing signal and controlsignal shown in FIG. 11.

DETAILED DESCRIPTION OF THE INVENTION

The objectives and advantages of the present invention will becomeapparent by describing in detail embodiments thereof with respect to theappended drawings. Like reference numerals in the drawings denote likemethod steps.

When external electric power EVC is applied, a semiconductor memorydevice sequentially receives a precharge command for precharging thesemiconductor memory device, a refresh command and a mode set command.These commands are given when external electric power EVC is applied tothe semiconductor memory device. When the semiconductor memory devicehas received these commands, it operates upon receipt of commandsrelated to operations. The first embodiment of the present inventionconcerns a method of generating an initializing signal by aninitializing circuit through these initial commands which are given whenthe external electric power EVC is applied to the semiconductor memorydevice.

Referring to FIG. 3, in a method 300 of generating an initializingsignal according to the first embodiment of the present invention, aprecharge command for precharging the semiconductor memory device issent to the semiconductor memory device after external electric power isapplied to the semiconductor memory device (step 310). Once theprecharge command is acknowledged, a signal for precharging is generatedto perform precharging operations. Apart from the prechargingoperations, the initializing signal is activated to a first level inresponse to the precharging command (step 320). The initializing signalis activated if a semiconductor memory device is configured to have acircuit in which one flag, i.e., a pulse-type signal, is generated.Here, the ‘first level’ may be a logic ‘high’ level or a logic ‘low’level.

After receiving the precharge command, the semiconductor memory devicereceives a refresh command for refreshing itself (step 330). Then, inresponse to the refresh command, the semiconductor memory device isrefreshed. Next, the semiconductor memory device receives a mode setcommand for setting an operational mode of the semiconductor memorydevice (step 340). The mode set command is a mode register set (MRS)command in a synchronous dynamic random access memory (DRAM) and a writeCAS before RAS (WCBR) in an asynchronous DRAM. Then, the semiconductormemory device may receive other commands and performs operationsaccording to the commands.

Next, according to the received mode set command, the initializingsignal is deactivated to a second level (step 350). Here, the secondlevel is logic ‘low’ if the first level is logic ‘high’, and vice versa,by which the initializing signal is characterized as a pulse signal. Thepulse signal serves as an initializing signal. Therefore, according tothe first embodiment of the present invention, the unstable operationsof the inner circuits can be prevented without the initializing circuit,thus reducing the layout area and power consumption of the initializingcircuit. Further, inner circuits otherwise operating unstably duringpower-up can be stabilized through the initializing signal generatedaccording to the above commands.

Referring to FIG. 4, a method 400 of generating an initializing signalaccording to a second embodiment of the present invention will bedescribed. The method according to the second embodiment of the presentinvention is different from that according to the first embodiment inwhich a single pulse signal is generated in response to a prechargecommand. That is, the semiconductor memory device receives the prechargecommand for precharging one or more banks thereof with external electricpower (step 410). Next, a refresh command and a mode set command aresequentially received by the semiconductor memory device. However, inaddition to these commands, the semiconductor memory device responds tothe received precharge command and generates an automatic pulse used asan initializing signal (step 420). The automatic pulse can be generatedby installing in the semiconductor memory device an automatic pulsegenerator that generates a pulse signal in response to the prechargecommand. The pulse signal generated by the automatic pulse generatorserves as an initializing signal generated by the initializing circuit.Therefore, the method of generating an initializing signal according tothe second embodiment produces the same effects as those according tothe first embodiment.

Referring to FIG. 5, a method 500 for generating an initializing signalaccording to a third embodiment of the present invention will bedescribed. The third embodiment is different from the first and secondembodiments of the present invention in that a pulse is generated inresponse to a mode set command. That is, after external electric poweris applied, the mode set command for setting an operational mode of asemiconductor memory device is received by the semiconductor memorydevice (step 510). Then, the semiconductor memory device responds to thereceived mode set command and generates an automatic pulse serving as aninitializing signal (step 520), which can be realized if an automaticpulse generator, which generates a pulse signal in response to the modeset command, is included in the semiconductor memory device. Here, as inthe first embodiment, the mode set command is a mode register set (MRS)command in a synchronous DRAM and a write CAS before RAS (WCBR) in anasynchronous DRAM. A pulse signal generated by the automatic pulsegenerator serves as an initializing signal generated by the initializingcircuit. Therefore, the effects of the third embodiment are the same asthose of the first and second embodiments.

Prior to the step 510, the method 500 for generating an initializingsignal according to the third embodiment of the present invention mayfurther include steps of receiving a precharge command for prechargingthe semiconductor memory device and of receiving a refresh command forrefreshing the semiconductor memory device.

Referring to FIG. 6, a method 600 of generating an initializing signalaccording to the fourth embodiment of the present invention will bedescribed. The fourth embodiment is different from the first throughthird embodiments in that it further includes an initializing circuitfor preventing initial unstable operations of inner circuits installedin a semiconductor memory device.

According to the method 600, an initializing circuit generates apreinitializing signal in response to external electric power (step610). The preinitializing signal is identical with the signal VCCHBoutput from the initializing circuit 100 shown in FIG. 1 and stabilizesthe inner circuits.

Next, the semiconductor memory device receives the mode set command(step 620) and generates an automatic pulse to be used as aninitializing signal in response to the preinitializing signal and thereceived mode set command (step 630). This can be realized by includingin the semiconductor memory device an automatic pulse generator thatgenerates a pulse signal in response to the preinitializing signal andthe mode set command. As a voltage level of external electric power EVCdecreases, that of the preinitializing signal decreases. Thus, while theexternal electric power is applied, the inner circuits can be morereliably initialized by a pulse signal which is generated in response toboth the preinitializing signal and the mode set command and serves asan initializing signal, rather than being responsive only to thepreinitializing signal. Here, as in the first embodiment, the mode setcommand is a mode register set (MRS) command in a synchronous DRAM and awrite CAS before RAS (WCBR) in an asynchronous DRAM. The methodaccording to the fourth embodiment of the present invention furtherincludes a step of turning off the initializing circuit in response to agenerated initializing signal. Therefore, power consumption due to theflow of a constant DC current through the initializing circuit afterpower-up can be reduced.

Between the steps 610 and 620, the method 600 according to the fourthembodiment of the present invention may further include steps ofreceiving the precharge command for precharging the semiconductor memorydevice and of receiving the refresh command for refreshing thesemiconductor memory device after the receipt of the precharge command.

FIG. 7 is a flowchart illustrating a method 700 for turning off theinitializing circuit according to a firth embodiment of the presentinvention. In the method 700, an initializing circuit generates aninitializing signal in response to external electric power applied tothe semiconductor memory device (step 710). The initializing signal isequal to a signal VCCHB output from the initializing circuit 100 shownin FIG. 1 and initializes inner circuits installed in the semiconductormemory device. Then, a precharge command for precharging thesemiconductor memory device is received by the semiconductor memorydevice (step 720). Thereafter, a refresh command and a mode set commandare sequentially received by the semiconductor memory device. At thistime, apart from these commands, the semiconductor memory deviceresponds to the received precharge command and turns off theinitializing circuit (step 730). This can be realized by implementing acircuit capable of turning off the initializing circuit in response tothe precharge command. Thus, after power-up, it is possible to reducepower consumption caused by a constant DC current flowing in theinitializing circuit.

In a method of turning off an initializing circuit according to a sixthembodiment of the present invention referring to FIG. 8, theinitializing circuit generates an initializing signal in response to theapplication of external electric power (step 810). The initializingsignal (which is the same as the signal VCCHB output from theinitializing circuit 100 shown in FIG. 1) initializing inner circuitsinstalled in the semiconductor memory device. Next, the semiconductormemory device receives a mode set command (step 820) and turns off theinitializing circuit in response to the received mode set command (step830). The turning off of the initializing circuit can be realized byimplementing a circuit that is capable of turning off the initializingcircuit in response to the mode set command. Accordingly, it is possibleto reduce power consumption caused by a constant DC current flowing inthe initializing circuit after power-up. Here, as in the firstembodiment, the mode set command is a mode register set (MRS) command ina synchronous DRAM and a write CAS before RAS (WCBR) in an asynchronousDRAM.

Between steps 810 and 820, the method of turning off the initializingcircuit according to the sixth embodiment of the present invention mayfurther include steps of receiving the precharge command for prechargingthe semiconductor memory device and receiving the refresh command forrefreshing the semiconductor memory device after receipt of theprecharge command.

FIG. 9 is a flow chart illustrating a method 900 of generating aninitializing signal according to a seventh embodiment of the presentinvention. In the method 900, a mode set command for initializing aninner circuit in a semiconductor memory device is received (step 910).Next, a control signal is generated in response to the received mode setcommand and used as the initializing signal (step 920).

The methods according to the first through sixth embodiments are toinitialize unstable operations of inner circuits during power-up of asemiconductor memory device. That is, a general initializing circuitinitializes inner circuits during power-up of a semiconductor memorydevice but cannot initialize them during operations of the semiconductormemory device that has already powered on. On the other hand, in themethod 900 according to the seventh embodiment, it is possible toinitialize inner circuits during the operation of a semiconductor memorydevice.

In the method 900, a mode set command for initializing inner circuits ina semiconductor memory device is received (step 910). The mode setcommand is a mode register set (MRS) command in a synchronous dynamicrandom access memory (DRAM) but is a Write Column address strobe (CAS)Before Row address strobe (RAS) (WCBR) in an asynchronous DRAM.

If there is a need to initialize a semiconductor memory device duringits operation, the MRS command for generating an initializing signal isfreshly asserted. That is, the existing MRS command is newly set togenerate the initializing signal.

After step 910, a control signal is generated in response to the modeset command and used as the initializing signal (step 920). That is, thenewly set MRS command generates the control signal. Here, the controlsignal is a signal that has a pulse shape. In general, an initializingsignal generated by an initializing circuit has a pulse shape, and thus,a control signal of a pulse shape can be also used as an initializingsignal.

In addition, the mode set command may be a signal that is applied to thesemiconductor memory device via an external pin. That is, a pin, whichcan apply a signal for initializing the semiconductor memory deviceduring its operation, is additionally attached to the external pin-outpackaging of a semiconductor memory chip. To initialize thesemiconductor memory device, a signal, which is the mode set command, isapplied to the semiconductor memory device via the external pin. In thiscase, the mode set command is a signal of a pulse shape rather than theMRS command.

FIG. 11 is a block diagram for explaining the method 900 shown in FIG. 9and FIG. 12 is a waveform diagram of an initializing signal and acontrol signal shown in FIG. 11. Referring to FIG. 11, an initializingcircuit 100 has the same structure as the existing initializing circuitfor generating an initializing signal VCCHB shown in FIG. 1. An innercircuit 1020 can be set to be initialized when the initializing signalVCCHB is at a high level or a low level, the levels depending on theinner structure of the initializing circuit 100. Here, as a matter ofconvenience, the inner circuit 1020 is described to be initialized inresponse to the high-level initializing signal VCCHB.

During power-up of the semiconductor memory device, a voltage level ofan external power source increases, and the level of the initializingsignal VCCHB, which is a signal output from the initializing circuit100, increases following the voltage level of the external power sourceand decreases to a low level when the outer power source reaches apredetermined voltage level (see FIG. 12(a)).

During the power-up operation, a control signal CTRLS is at a low leveland the initializing signal VCCHB is at a high level. Thus, a high-levelinitializing control signal VCCHB_A is generated by an OR means 1010(depicted as a NOR gate), and the inner circuit 1020 is initialized inresponse to the initializing control signal VCCHB_A.

If the level of the initializing signal VCCHB is changed to be a lowlevel, then the initializing control signal VCCH_A is also at a lowlevel. If the initializing control signal VCCHB_A is at a low level,then the inner circuit 1020 is not initialized.

If there is a need to initialize the semiconductor memory device duringits operation, a mode set command is generated. As previously mentioned,the mode set command may be the MRS command or WCBR. In response to themode set command, a control signal CTRLS, which has a pulse shape, isgenerated.

At a rising edge of the control signal CTRLS, the level of theinitializing control signal VCCHB_A is changed to be a high level by theOR means 1010 and the inner circuit 1020 is initialized, whereas at afalling edge of the control signal CTRLS, the level of the initializingcontrol signal VCCHB_A is changed to a low level.

Waveforms of the initializing signal VCCHB, the control signal CTRLS andthe initializing control signal VCCHB_A are shown in FIG. 12(a), (b),and (c), respectively.

In FIG. 11, the structure of the inner circuit 1020 can be modified tobe initialized by applying the control signal CTRLS directly to theinner circuit 1020 without the initializing circuit 100. In this case,the inner circuit 1020 also operates in response to the mode set commandor the control signal CTRLS as described above, and thus a detaileddescription thereof will be omitted here.

FIG. 10 is a flowchart illustrating a method 950 of generating aninitializing signal according to an eighth embodiment of the presentinvention. In accordance with the method 950, a precharge command forprecharging a semiconductor memory device is received (step 960). Afterstep 960, a mode set command for initializing inner circuits in thesemiconductor memory device is received (step 970). Next, in response tothe mode set command, a control signal is generated and used as theinitializing signal (step 980).

The precharge command can be generated during the operation of thesemiconductor memory device as well as during power-up thereof. Thegeneration of a precharge command occurs when the semiconductor memorydevice is carrying out a write or read operation, except when thesemiconductor memory device is turning on.

Therefore, the method 950 according to the eighth embodiment is togenerate an initializing signal, as in the method 900 according to theseventh embodiment, upon receipt of a precharge command during theoperation of the semiconductor memory device. The method 950 is the sameas the method 900, except that the state of the semiconductor memorydevice is determined with the generation of the precharge signal. Thus,a detailed description of the method 950 will be omitted here.

As described above, the methods for generating an initializing signalaccording to the present invention have advantages of reducing powerconsumption and the layout area that the initializing circuit, as wellas providing more stable and reliable initializing operation of theinitializing circuit itself.

While the present invention has been particularly shown and describedwith reference to the preferred embodiment thereof, the presentinvention is not restricted to the above embodiment. Further, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention as defined by the appended claims.

1. A method of generating an initializing signal for initializing aninner circuit in a semiconductor memory device, the method comprising:(a) receiving a mode set command for initializing the inner circuitafter receiving a precharge command; and (b) generating a control signalin response to the received mode set command and using the controlsignal as the initializing signal.
 2. The method of claim 1, wherein themode set command is a signal applied to the semiconductor memory devicevia an external pin.
 3. The method of claim 1, wherein the mode setcommand is a mode register set (MRS) command in a synchronous dynamicrandom access memory (DRAM).
 4. The method of claim 1, wherein the modeset command is a Write Column address strobe (CAS) Before Row addressstrobe (RAS) (WCBR) in an asynchronous dynamic random access memory(DRAM).
 5. A method of generating an initializing signal forinitializing an inner circuit in a semiconductor memory device, themethod comprising: (a) receiving a precharge command for precharging thesemiconductor memory device; (b) receiving a mode set command forinitializing the inner circuit after receipt of the precharge command;and (c) generating a control signal in response to the received mode setcommand, and using the control signal as the initializing signal.
 6. Themethod of claim 5, wherein the mode set command is a signal applied tothe semiconductor memory device via an external pin.
 7. The method ofclaim 5, wherein the mode set command is a mode register set (MRS)command in a synchronous dynamic random access memory (DRAM).
 8. Themethod of claim 5, wherein the mode set command is a Write Columnaddress strobe (GAS) Before Row address strobe (RAS) (WCBR) in anasynchronous dynamic random access memory (DRAM).